The present invention relates to high-breakdown-voltage semiconductor devices (hereinafter referred to as “high-voltage semiconductor devices”), and more particularly relates to high-voltage semiconductor devices for controlling inverters.
A system for controlling inverters in lighting applications is illustrated in FIG. 16, as an example in which a conventional inverter-control high-voltage semiconductor device is employed. FIG. 16 schematically illustrates the structure of the lighting inverter-control system.
The inverter control system shown in FIG. 16 includes: an LC resonance circuit including a fluorescent lamp 100; high-breakdown-voltage n-channel power MOSFETs 101 and 102 for supplying power to the fluorescent lamp 100; a high-voltage-end drive circuit 105 for driving the high-voltage n-channel power MOSFET 101; and a low-voltage-end drive circuit 106 for driving the high-voltage n-channel MOSFET 102. The high-voltage-end drive circuit 105 is constituted by a high-voltage semiconductor device for inverter control. Here, the high-voltage power MOSFETs 101 and 102 are discrete elements. The inverter control system further includes: a high-voltage diode 104 for applying a source voltage V2 to the high-voltage-end drive circuit 105; a capacitor 103; a fluorescent-lamp-drive high-voltage power supply terminal 110; a power supply terminal 107 for the low-voltage-end drive circuit 106; and an output terminal 109 for driving the fluorescent lamp.
V1, applied for fluorescent lamp drive to the high-voltage power supply terminal 110, is a direct current voltage rectified from the alternating current power source, and V1 is a high voltage that is at maximum on about 600 V. Meanwhile, V3, applied to the power supply terminal 107 for the low-voltage-end drive circuit 106, is a power-supply voltage for the low-voltage-end drive circuit 106, and is a low voltage normally on about 15 V. V2, applied to a power supply terminal 108 for the high-voltage-end drive circuit 105, is defined by the low-voltage-end drive circuit voltage V3, the high-voltage diode 104, the capacitor 103, and the n-channel high-voltage power MOSFETs 101, 102. And V2 changes within a range from about the 15 V voltage of V3 to on about a 615 V voltage that is (V1+V3), in accordance with the ON/OFF functioning of the high-voltage power MOSFETs 101 and 102.
Next, the operation of the lighting inverter control system will be described.
First, in its initial state in which V3=15 V and V1=600 V are applied, an output terminal voltage V4 for driving the fluorescent lamp 100 is normally set close to the ground potential GND. So, in this state, the capacitor 103 is charged by powering the high-voltage diode 104 in the forward direction, and then V2 is set to a voltage given by subtracting the forward direction voltage of the high-voltage diode 104 from V3=15 V.
Next, the high-voltage n-channel power MOSFET 102 is turned OFF by a low-voltage-end control signal, and the high-voltage power MOSFET 101 is turned ON by a high-voltage-end control signal. Thus, the capacitor in the LC resonance circuit including the fluorescent lamp 100 is charged. At this point, when the high-voltage power MOSFET 101 is turned ON, the output terminal voltage V4 for driving the fluorescent lamp 100 elevates from near the ground potential GND to a potential on about V1=600 V (a voltage given by subtracting the ON voltage of the high-voltage MOSFET 101 from the voltage V1). Therein, the capacitor 103 has been charged and thus the potential difference between the voltage V2—which will substantially be the supply voltage for the high-voltage-end drive circuit 105—and the output terminal voltage V4 may be kept at the initial voltage of about V3—which is a potential on about 15 V (the voltage given by subtracting the forward direction voltage of the high-voltage diode 104 from V3). In this manner, the voltage V2 is elevated from a potential of about V3=15 V to a potential on about(V1+V3)=615 V.
Thereafter, the high-voltage n-channel power MOSFET 101 is turned OFF by the high-voltage-end control signal and the high-voltage n-channel power MOSFET 102 is turned ON by the low-voltage-end control signal, whereby the fluorescent lamp 100 is discharged. At this point, when the high-voltage power MOSFET 102 is turned ON, the output terminal voltage V4 for driving the fluorescent lamp is lowered from a potential of about V1=600 V (the voltage given by subtracting the ON voltage of the high-voltage MOSFET 101 from the voltage V1) to near the ground potential GND (a potential given by adding the ON voltage of the high-voltage MOSFET 102 to the ground potential GND). Therein, the capacitor 103 has been charged and thus the potential difference between the voltage V2—which will substantially be the supply voltage for the high-voltage-end drive circuit 105—and the output terminal voltage V4 may be kept at the initial voltage of about V3=15 V (the voltage given by subtracting the high-voltage diode 104 forward voltage from V3). In this manner, the voltage V2 is lowered from a potential on about (V1+V3)=615 V to about V3=15 V.
The above-described operation is a single-cycle functioning of the fluorescent-lamp-containing LC resonance circuit, during which it is charged and discharged.
In recent years, there have been studies on integrating the low-voltage-end drive circuit (106 in FIG. 16), the high-voltage-end drive circuit (105 in FIG. 16), and other control circuits in an inverter control system used in lighting uses. A high-voltage-end drive circuit of this type (105 in FIG. 16) is a circuit block that is generally referred to as a “floating block,” and its power supply terminal 108 is not biased by a fixed voltage, and the terminal 108 is electrically floating. FIG. 17 illustrates the cross-sectional structure of a floating block that has been integrated.
The floating block depicted in FIG. 17 includes: a p-type semiconductor substrate 1; a lightly n-type doped semiconductor region 2 formed in the substrate 1; an n-type doped region 3; a p-type doped isolating region 4 that electrically isolates adjacent circuit elements; a heavily n-type doped contact region 6 for applying a potential of the power supply terminal 108 to the semiconductor region 2; a metal electrode 25 for applying the potential to the semiconductor region 2; and a metal electrode 33 for applying a potential to the isolating region 4 and the p-type semiconductor substrate 1.
A thin oxide film 15 and a thick oxide film 16 are formed between the isolating region 4 and the contact region 6. On the oxide films 15 and 16, plate electrodes 17b, 18b and 19b, which are made of polysilicon, are formed; plate electrode 17b is set at a potential equal to that of metal electrode 33; plate electrode 18b is electrically floating; and plate electrode 19b is connected with metal electrode 25. An interlayer dielectric film 34 is deposited over the plate electrodes 17b, 18b and 19b; and metal electrodes 40 and 41 that are electrically floating are formed on the interlayer dielectric film 34. A protective film 35 is formed over the metal electrodes 40 and 41, and a plastic encapsulant (resin for encapsulation) 36 is further formed on the protective film 35.
In the structure shown in FIG. 17, CMOSs, capacitors, resistors, and like elements constituting a high-voltage-end drive circuit are formed in the region surrounded by the contact region 6. This region will hereinafter be referred to as the “high-voltage-end drive circuit element region.”
In the high-voltage-end drive circuit element region shown in FIG. 17, an n-channel MOS p-type doped body region 7, n-channel MOS n-type source and drain regions 8 and 9 that are formed in the p-type doped body region 7, and an n-channel MOS polysilicon gate electrode 22, each of which constitutes a part of the high-voltage-end drive circuit, are formed. Source and drain metal electrodes 26 and 27 are connected to the n-type source and drain regions 8 and 9. Further, p-channel MOS p-type source and drain regions 10 and 11, a p-channel MOS polysilicon gate electrode 23, and also p-channel MOS source and drain metal electrodes 28 and 29, each of which constitutes a part of the high-voltage-end drive circuit, are formed. These components make up a CMOS transistor element.
Moreover, a p-type doped region 12 that serves as one electrode of the capacitor element, a metal electrode 30 connected to the p-type doped region 12, and a polysilicon electrode 24 that serves as the other electrode of the capacitor element are formed in the high-voltage-end drive circuit region, making up a capacitor element. Further, therein, a p-type doped resistor 13 that constitutes a part of the high-voltage-end drive circuit, and metal electrodes 31 and 32 for the p-type doped resistor 13 are formed, making up a resistor element.
In the structure shown in FIG. 17, the source voltage V2 from the high-voltage-end drive circuit shown in FIG. 16 is applied to the metal electrode 25. The ground potential GND is applied to the metal electrode 33 that is connected to the isolating region 4. Herein, the n-channel MOS p-type doped body region 7 constituting a part of the CMOS is put to the potential V4 of the high-voltage-end drive circuit.
As can be understood from the above-described operation of the lighting inverter control system, the metal electrode 25, polysilicon plate electrode 19b, and n-doped contact region 6, which are given the voltage V2, vary from a low voltage of about 15 V to a high voltage of about 615 V. On the other hand, since the potential V4 from FIG. 16 becomes the potential of the n-channel MOS p-type doped body region 7 in FIG. 17, the potential of the p-type doped body region 7 varies from near the ground potential GND to a potential on about V1=600 V. Therein, the difference in potential between the p-type doped body region 7, and the metal electrode 25, plate electrode 19b, and heavily doped contact region 6 is kept at about 15 V.
Accordingly, a high voltage on about 615 V is applied to the p-n junctions in between the p-type semiconductor substrate 1 and isolating region 4, and the n-type semiconductor region 2. In the structure shown in FIG. 17, the plate electrodes 17b, 18b and 19b are a variety of field plates, and the plate electrodes are capacitively coupled to the floating metal electrodes 40 and 41 through the interlayer dielectric film 34 formed over the electrodes 17b, 18b and 19b. And the plate electrodes, thereby, divides the potential difference that is across the metal electrode 25 and plate electrode 17b, so that the distribution of the potential at the surface of the semiconductor region 2 is not concentrated locally.
FIG. 18 is a plan view depicting the structure of the floating block shown in FIG. 17. For ease of illustration, only the polysilicon plate electrodes 17b, 18b and 19b, metal electrodes 25, 33, 40 and 41 and contact region 6 are set out in FIG. 18.
Each of the polysilicon plate electrodes 17b, 18b and 19b has a predetermined width and is in the shape of an approximately rectangular loop having arcuate corners. Each of the metal electrodes 25, 33, 40 and 41, located over the plate electrodes 17b, 18b and 19b, also has a predetermined width and is also in the shape of an approximately rectangular loop having arcuate corners, but one section thereof is cut away. The cut-away sections are formed with a metal wiring 49 for propagating the high-voltage-end drive circuit control signal. Thus, elements for the high-voltage-end drive circuit are disposed in the region surrounded by the metal electrode 25 and the contact region 6.
Next, how the structure illustrated in FIGS. 17 and 18 realizes a high-voltage semiconductor device will be described. FIG. 19 illustrates parasitic capacitances present in the structure shown in FIG. 17. Meanwhile FIG. 20 illustrates profile of the distribution of potentials (“potential profile” hereinafter) when a high voltage (e.g., 600 V) is applied to the device having the structure shown in FIG. 17. In FIG. 20, dashed lines indicate equipotential lines for each of the potentials.
As shown in FIG. 19, a parasitic capacitance C1 is present between the plate and floating metal electrodes 17b and 40; a parasitic capacitance C2 is present between the floating metal and plate electrodes 40 and 18b; a parasitic capacitance C3 is present between the plate and floating metal electrodes 18b and 41; and a parasitic capacitance C4 is present between the floating metal and plate electrodes 41 and 19b. A series circuit, formed by these parasitic capacitances C1 through C4, acts to divide the voltage, thereby establishing a potential at the plate electrode 18b and imparting a suitable potential profile in the semiconductor region 2. Enabling an appropriate potential profile to be imparted in this way realizes a semiconductor device having a high breakdown voltage. It should be noted that parasitic capacitances C5 and C6, occurring between the metal electrodes 40 and 41 and plastic encapsulant 36 shown in FIG. 19, are normally considered non-existent as will be described later.
Referring next to FIG. 20, a potential profile of the conventional high-voltage semiconductor device at room temperature is schematically illustrated. The present inventors confirmed that the potential profiles illustrated in FIG. 20, and results of simulations that the inventors carried out showed similar tendencies.
The potential profile illustrated in FIG. 20 was obtained wherein a ground potential of 0 V was applied to the substrate 1, isolating region 3, plate electrode 17b and metal electrode 33, and a voltage of 600 V was applied to the contact region 6, plate electrode 19b and metal electrode 25. As may be understood form FIG. 20, when the same 600 V high potential as that of the contact region 6 is applied to the plate electrode 19b, an intermediate potential between 600 V and 0 V will be imparted to the plate electrode 18b. Accordingly, the equipotential lines, representing the potential profile of the semiconductor region 2, extend vertically to the surface of the semiconductor region 2, and are distributed almost equidistantly from each other. This as a result lets the concentration of electric field in the semiconductor region 2 be reduced, which maintains the high breakdown voltage characteristics of the transistor.
However, if the device is operated at an elevated ambient temperature of 150° C. while a high voltage of 500 V or more (e.g. 600 V) is still being applied to the metal electrode 25, then a phenomenon arises in which the breakdown voltage (i.e., the breakdown voltage between the terminal 108 in FIG. 16 to which the voltage V2 is applied, and the ground potential GND) between the metal electrodes 25 and 33 deteriorates. This phenomenon can be simulated by a life test called “high-temperature bias test”. When the voltage applied to the metal electrode 25 is increased in the high-temperature bias test, the deterioration in breakdown voltage becomes striking; when the applied voltage is reduced, the breakdown voltage deterioration tends to be less.
The mechanism behind the deterioration in breakdown voltage between the metal electrode 25 and GND in the high-temperature bias test is unclear and does not go beyond the realm of speculation. Nevertheless, the following may be speculated.
In general, a semiconductor chip is packaged with a plastic encapsulant to prevent water or moisture from entering the plastic package. However, novolac epoxy resin, a typical plastic encapsulant, contains 0.9% to 1.6% hydroxyl (OH) groups. At elevated temperatures, these OH groups are activated and the plastic encapsulant 36, which is usually considered an insulator, becomes semi-insulating (i.e., electrically conductive at high resistance).
In a high-voltage semiconductor device, a semiconductor chip is normally packaged with the plastic encapsulant 36 and multiple pads (not shown) on the chip are usually electrically connected to multiple external terminals (not shown) via fine metal wirings (not shown). The 0 V that is the ground potential, 600 V that is the supply voltage, and the control signal are applied to the fine metal wirings, respectively. Accordingly, when the plastic encapsulant 36 becomes semi-insulating through the above-described action, an intermediate potential between 600 V and 0 V is presumed to be applied to the surface of the protective film 35. The intermediate potential is variable depending on the layout of the semiconductor chip in question. For example, where a grounding pad (not shown) is provided near the insulated-gate transistor on the chip, and a power-source pad (not shown) is provided in a position distant from the grounding pad, part of the plastic encapsulant 36 over the insulated-gate transistor might be at an intermediate potential of about 100 V. Taking such factors together and hypothesizing that during the high-temperature bias test the interface between the plastic encapsulant 36 and the protective film 35 on the semiconductor chip would have a potential of 100 V, the present inventors investigated what the potential distribution would be like in that situation.
The potential profile during the high-temperature bias test will be described in the following with reference to FIG. 21. FIG. 21 illustrates a posited potential profile during a high-temperature bias test in which the temperature was raised under the same bias voltage conditions as for the profile at room temperature, illustrated in FIG. 20. In FIG. 21, each dashed line indicates an equipotential line.
In the state shown in FIG. 21, the floating metal electrode 40 is accompanied not only by the parasitic capacitances C1 and C2, but also by another parasitic capacitance C5 formed between the floating metal electrode 40 and plastic encapsulant 36 (see FIG. 19). Likewise, the other floating metal electrode 41 is accompanied not only by the parasitic capacitances C3 and C4, but also by another parasitic capacitance C6 formed between the floating metal electrode 41 and plastic encapsulant 36. Accordingly, if the parasitic capacitance C5 or C6 has a value approximately equal to that of the sum of parasitic capacitances C1+C2 or C3+C4, then the plastic encapsulant 36 becomes semi-insulating during the high-temperature bias test. When the region of the plastic encapsulant 36 over the floating metal electrodes 40 and 41 comes to have a potential of 100 V, the potential of the floating metal electrode 41, which was about 450 V at room temperature, lowers to about 300 V due to the influence of the parasitic capacitance C6. In the same way, the potential of the floating metal electrode 40, which was about 150 V at room temperature, decreases to about 130 V owing to the influence of the parasitic capacitance C5. In response to this, the potential at the plate electrode 18b, which was about 300 V at room temperature, also decreases to 200 V. As a result, among the equipotential lines transecting the interface between the semiconductor region 2 and the oxide film 16, those that are 200 V or more bend toward the contact region 6, as indicated in FIG. 21, and thus the potential of the oxide film 16 side at the interface becomes negative with respect to the surface potential of the n-type semiconductor region 2.
Here, as far as the interface between the n-type semiconductor region 2 and oxide film 16 is concerned, it has been reported (“Reliability Technology for Semiconductor Devices,” Japan Union of Scientists and Engineers Publishing Co.) that when in a high-temperature environment the potential on the oxide film 16 side becomes negative, the Si—H and Si—OH bonds in the interface are broken, creating positive fixed charges. When this sort of phenomenon occurs, giving rise to positive fixed charges in the interface between the semiconductor region 2 and the oxide film 16, negative mobile charges are also created in the oxide film 16. The negative mobile charges in the oxide film 16 are with the passage of time attracted little by little to the positive high potential of the metal electrode 25. As a result, the negative mobile charge density increases locally in a region of the oxide film 16 near the metal electrode 25, while the positive fixed charge density increases in the region where the negative mobile charges were originally created. Since a great number of negative charges exist in that region of the oxide film 16 over the interface and near the metal electrode 25, holes are attracted from the semiconductor region 2 toward that region. As a result, the surface of the n-type semiconductor region 2 changes into the opposite type, or p-type, thus forming a p-type inversion layer 43. Moreover, the region where the positive fixed charges remain attracts electrons from the semiconductor region 2, and thus the electron density increases locally in the area of the semiconductor region 2. As a result, an n-type accumulation layer 42 is formed near the surface of the semiconductor region 2.
Where the p-type inversion layer 43 and n-type accumulation layer 42 are formed in this way near the surface of the semiconductor region 2 as shown in FIG. 21, the electric field is locally concentrated where the p-type inversion layer 43 is near the contact region 6. It is assumed that over time, the breakdown voltage of the high-voltage semiconductor device deteriorates as a result.
Next, as a second conventional example, another known high-voltage semiconductor device will be described with reference to FIGS. 22 and 23. FIG. 22 illustrates in cross-section the chief components of a high-voltage semiconductor device according to the second conventional example. FIG. 23 illustrates parasitic capacitances in the structure illustrated in FIG. 22. It should be understood that regions in FIGS. 22 and 23 that are the same as in the first conventional example (FIG. 17) are assigned the same reference numerals, whose description will be omitted.
The device shown in FIG. 22 further includes p-type guard ring regions 44 and 45 that serve to increase its breakdown voltage. Unlike the device of the first conventional example shown in FIG. 17, the device of the second conventional example does not have the floating metal electrodes 40 and 41, but rather includes p-type guard ring regions 44 and 45 in the n-type semiconductor region 2.
In the conventional semiconductor device shown in FIG. 23, a parasitic capacitance C7 is present between the plate electrode 17b and guard ring region 44; a parasitic capacitance C8 is present between the guard ring region 44 and plate electrode 18b; a parasitic capacitance C9 is present between the plate electrode 18b and guard ring region 45; and a parasitic capacitance C10 is present between the guard ring region 45 and plate electrode 19b. A series circuit due to these parasitic capacitances C7 through C10 divides the voltage applied between the metal electrodes 25 and 33, establishing potentials in the guard ring regions 44 and 45, and plate electrode 18b. At least, this is in all likelihood the case at room temperature.
When the device with this structure is subjected to a high-temperature bias test as in the first conventional example, the plastic encapsulant 36 becomes semi-insulating. As a result, the surface of the protective film 35 comes to have an intermediate potential between 600 V and 0 V. If the intermediate potential were to be a low about 100 V, then the potential at the plate electrode 18b, which is about 300 V at room temperature, would lower to about 200 V, due to the existence of a parasitic capacitance C11 between the plastic encapsulant 36 and plate electrode 18b. In that case, the p-type inversion layer 43 occurs between the guard ring regions 44 and 45, making continuity between them. As a result, the breakdown voltage of the high-voltage semiconductor device is degraded.